Flip-Flops (SR,D,JK,T flip-flops)

                  The storage elements employed in clocked sequential circuits are called flip-flops, A flipflop is a binary cell capable of storing one bit of information. It has two outputs one for the normal value and one for the complement value of the bit stored in it. A flip- flop maintains a binary state until directed by a clock pulse to switch stare. The difference among various types of flip-flops is in the number of inputs they possess and in the manner in which the inputs affect the binary state.





SR flip-flop:

                   This SR(set or reset) flip-flop has three inputs, labeled S(for set)m R(for reset)m and c(for clock)[ we take c if  it is asynchronous system]. It has one output Q and some times the flip-flop has a complemented output, which is indicated with a small circle at the other output terminal.

                    If  R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates

Observe the following table to under stand input output signals of SR flip-flop.

S R Action(Q) 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Restricted combination

D flip-flop:

            The D(data or delay) flip-flop is a slight modification of the SR flip-flop. An SR flip-flop is converted to a D flip flop by inserting an inverter between S and R and assigning the symbol D to the single input. The D input is  sampled during the occurrence of a clock transition from 0 to 1. if D=1 the output of the flip flop goes to the 1 stare but if D=0 the output of the flip flop goes to the 0 state.

D filp flop based on SR NAND

D flip flop based on SR NOR

D	Input
E	Enable/clock
Q	Output
Q	Inverse of Q

JK flip flop:

               A JK flip flop is a refinement of the SR flip flop in that indeterminate condition of the sr type is defined in the JK type. INputs J and K behave like inputs S and R to set and clear the flip-flop tespectively. When inputs J and K are both equal to 1 a clock transition switches the outputs of the flip flop to their complement stare.i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

JK flip-flop

T-Flip Flop:

                  Another kind of flip flop is T(toggle) flip flop. This flip flop obtained form a JK type. If you know the jk flip flop it is very simple to know t flip flop. If we connect the J and k inputs in jk flip flop we obtain T flip flop.

T flip flop

Advanced Electronics 8